Yea, I've seen that, but they either seem to be in various states of
not-done-ness or they are marked as done, but they are for different RAM
configurations than the single chip that is on the 7300.
For example, I've been looking at one that appears complete, but it appears to
be hardwired for a two chip configuration (32 bits of data instead of the 16 we
have) and I don't see any way to easily configure the timings it uses either.
A different one gives me control of the timings, but it appears so
convoluted(and is in VHDL which I can barely read on a good day) that I can't
determine how to even interface with it.
If I at least had decent RTL for the various transfers and refresh of PC-133
ram I could probably implement my own controller, but I'm having a hell of a
time even finding that information presented in a way that I can understand it
well enough to give it a go. Datasheets for the chip on the TS-7300 seem to
largely skim over the actual transfer details to a large degree assuming that
you just know how PC-100 or PC-133 ram is supposed to work. I've even looked
at datasheets for other comparable chips with the same configuration since the
timing should mostly be the same and I've struck out there as well.
James
--- In Ian Thompson <> wrote:
>
> James
>
> There are some designs for SDRAM controllers in www.opencores.org.
>
> Ian T.
>
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