<*>[Attachment(s) from David Preza H included below]
Right now I am working in some code to control 6 pwm, so I can move some TULA
(piezoelectric actuators) with the TS7500. The code is still in work, but I
will attach a verilog file to generate a PWM based on a clk, number of ticks to
generate the frequency, and numbers of ticks to get the duty cicle. The
i_enable needs to be high in order to actually produce an output.
I am still working in the interaction with the Wishbone and the Lattice FPGA on
the TS7500. However, I think you can override the functionality of some pins,
if you create new output pads, with the output of the code, and when you map
which one goes to which pad, you can just detach the pins you don't use (I did
it for pin 40, and the test was successful). However, don't forget to keep the
other pads and pins in their place.
I am not a hardware designer, neither a verilog expert, but I hope the code
helps you. I think the next weekend I will finish the wishbone interaction part.
Regards,
Enrique
<*>Attachment(s) from David Preza H:
<*> 1 of 1 File(s)
http://groups.yahoo.com/group/ts-7000/attachments/folder/1167326511/item/list
<*> generador_pwm.v
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