SPI Program:
#include "peekpoke.h"
#include<assert.h>
#include<unistd.h>
#include<sys/types.h>
#include<sys/mman.h>
#include<stdio.h>
#include<fcntl.h>
#include<stdlib.h>
#include <stdint.h>
#define MEMLOC 0x80840000
#define DIO2MASK 0x02
#define maskit 0xFD
#define changebit1 0xFD
#define ddr_new_mask 0xff
#define SSPCR0 0x808a0000
#define base 0x808a0000
#define SSPCPSR (volatile unsigned int*)(base+16)//0x808a0010 // Clock
Prescale Register
#define SSPDR (volatile unsigned int*)(base+32)//0x808a0008 // FIFO DR
Register
int fd,diobits,diobits_post_change, dio_direction_bits,
dio_direction_bits_post_change;
int main ()
{
volatile unsigned long int *memloc;
fd = open("/dev/mem", O_RDWR|O_SYNC);
if (fd == -1){
perror("open(/dev/mem):");
return 0;
}
memloc = mmap(0, getpagesize(), PROT_READ|PROT_WRITE, MAP_SHARED, fd, MEMLOC);
assert(memloc != MAP_FAILED);
diobits = PEEK8( (unsigned long)(memloc + 0x04));
printf("Starting with DR Bits Equal to : %x\n", diobits);
/* Reset all DIO bits to low */
/* Poke it - change dio data bit to 0 or 0x00 hex */
printf("Reseting all DIO bits to low\n");
POKE8( (unsigned long)(memloc + 0x04), 0x00);
diobits_post_change = PEEK8( (unsigned long)(memloc + 0x04));
printf("Did it work?\n");
if (diobits_post_change == 0x00)
{
printf("Yes!, DIO bits are now %x\n", diobits_post_change);
}
else
{
printf("Nope! Now DR Bits Equal %x\n", diobits_post_change);
exit(1);
}
/* Set DDR to output for all DIO pins */
dio_direction_bits = PEEK8( (unsigned long)(memloc + 0x14));
printf("Starting with DDR Bits Equal to : %x\n", dio_direction_bits);
POKE8( (unsigned long)(memloc + 0x14), 0xff);
dio_direction_bits_post_change = PEEK8( (unsigned long)(memloc + 0x14));
printf("Did it work?\n");
if (dio_direction_bits_post_change & 0xff)
{
printf("Yes!, DIO bits are now %x (all DIOs are set for
output)\n", dio_direction_bits_post_change);
}
else
{
printf("Nope! Now DR Bits Equal %x\n",
dio_direction_bits_post_change);
}
/****************************/
/* Map SSP Base Memory Page */
/****************************/
volatile unsigned long int *sspcr0;
sspcr0 = mmap(0, getpagesize(), PROT_READ|PROT_WRITE, MAP_SHARED, fd, SSPCR0);
assert(sspcr0 != MAP_FAILED);
/*********************************************************/
/* Enable SSP (SSE bit) - SSP Initialization Step 1 of 4 */
/*********************************************************/
int sspsse_check;
/* Is SSPSSE bit set? */
sspsse_check = PEEK8( (unsigned long)(sspcr0 + 0x04));
if (sspsse_check & 0x10)
{
printf("SSPSSE bit already set\n");
printf("8 bits of SSPCR1 is mapped to : %04x\n", sspsse_check);
}
else
{
printf("SSPSSE bit not set, but setting it now\n");
/* Configure SSPCR1 Register */
POKE8( (unsigned long)(sspcr0 + 0x04), 0x10);
/* Check SSPCR1 Changes */
sspsse_check = PEEK8( (unsigned long)(sspcr0 + 0x04));
printf("8 bits of SSPCR1 (SSPSSE bit ) is now mapped to =
%04x\n", sspsse_check);
}
/****************************************************************/
/* Configure Control Registers - SSP Initialization Step 2 of 4 */
/****************************************************************/
/*****************************/
/* Configure SSPCR0 Register */
/*****************************/
unsigned long int sspcr0_check;
/* What SSPCR0 Register has to start with */
sspcr0_check = PEEK16( (unsigned long)(sspcr0));
printf("16 bits of SSPCR0 is mapped to : %04x\n", sspcr0_check);
/* Configure SSPCR0 Control Register */
POKE16( (unsigned long)(sspcr0), 0x001f);
/* Check SSPCR0 Changes */
sspcr0_check = PEEK16( (unsigned long)(sspcr0));
printf("16 bits of SSPCR0 is now mapped to = %04x\n", sspcr0_check);
/*****************************/
/* Configure SSPCR1 Register */
/*****************************/
unsigned long int sspcr1_check;
/* What SSPCR1 Register has to start with */
sspcr1_check = PEEK8( (unsigned long)(sspcr0 + 0x04));
printf("8 bits of SSPCR1 is mapped to : %04x\n", sspcr1_check);
/* Configure SSPCR1 Register */
POKE8( (unsigned long)(sspcr0 + 0x04), 0x10);
/* Check SSPCR1 Changes */
sspcr1_check = PEEK8( (unsigned long)(sspcr0 + 0x04));
printf("8 bits of SSPCR1 is now mapped to = %04x\n", sspcr1_check);
/******************************/
/* Configure SSPCPSR Register */
/******************************/
unsigned long int sspcpsr_check;
/* What SSPCPSR Register has to start with */
sspcpsr_check = PEEK8( (unsigned long)(sspcr0 + 0x10));
printf("8 bits of SSPCPSR is mapped to : %04x\n", sspcpsr_check);
/* Configure SSPCPSR Register */
POKE8( (unsigned long)(sspcr0 + 0x10), 0x02);
/* Check SSPCPSR Changes */
sspcpsr_check = PEEK8( (unsigned long)(sspcr0 + 0x10));
printf("8 bits of SSPCPSR is now mapped to = %04x\n", sspcpsr_check);
/*************************************************************/
/* Clear the SSP enable bit - SSP Initialization Step 3 of 4 */
/*************************************************************/
unsigned long int sspsse_clear_check;
/* Is the SSP still enabled? */
sspsse_clear_check = PEEK8( (unsigned long)(sspcr0 + 0x04));
printf("8 bits of SSPCR1 is mapped to : %04x (Should be enabled with 0x10)\n",
sspcr1_check);
/* Configure SSPCR1 Register */
POKE8( (unsigned long)(sspcr0 + 0x04), 0x00);
/* Check SSPCR1 Changes */
sspsse_clear_check = PEEK8( (unsigned long)(sspcr0 + 0x04));
printf("8 bits of SSPCR1 is now mapped to = %04x (Should be disabled with
0x00)\n", sspsse_clear_check);
/*********************************************************/
/* Enable SSP (SSE bit) - SSP Initialization Step 4 of 4 */
/*********************************************************/
unsigned long int sspsse_reenable_check;
/* Is the SSP still disabled? */
sspsse_reenable_check = PEEK8( (unsigned long)(sspcr0 + 0x04));
printf("8 bits of SSPCR1 is mapped to : %04x (Should be enabled with 0x00)\n",
sspsse_reenable_check);
/* Configure SSPCR1 Register */
POKE8( (unsigned long)(sspcr0 + 0x04), 0x10);
/* Check SSPCR1 Changes */
sspsse_reenable_check = PEEK8( (unsigned long)(sspcr0 + 0x04));
printf("8 bits of SSPCR1 is now mapped to = %04x (Should be enabled with
0x10)\n", sspsse_reenable_check);
/***********************/
/* Make SSP Conversion */
/***********************/
printf("Starting SSP conversion\n");
POKE8( (unsigned long)(memloc + 0x04), 0x02);
diobits_post_change = PEEK8( (unsigned long)(memloc + 0x04));
printf("Did it work?\n");
if (diobits_post_change & 0x02)
{
printf("Yes!, DIO bits are now %x\n", diobits_post_change);
printf("Sleeping for 1 second ....\n");
sleep(1);
printf("Disabling DIO 2 (Changing back to low)\n");
POKE8( (unsigned long)(memloc + 0x04), 0x00);
diobits_post_change = PEEK8( (unsigned long)(memloc + 0x04));
printf("DIO Bits now equal %x, should be 0x00\n",
diobits_post_change);
}
else
{
printf("Nope! Now DR Bits Equal %x\n", diobits_post_change);
exit(1);
}
/***********************/
/* Read SSPDR Resgiter */
/***********************/
volatile int sspdr_read;
//volatile int *sspdr_read_ptr;
/* SSPDR Output */
sspdr_read = PEEK16( (unsigned long)(sspcr0 + 0x08));
//*sspdr_read_ptr = (SSPCR0 + 0x08);
printf("16 bits of SSPDR is mapped to : %04x\n", sspdr_read);
//printf("sspdr_read_ptr points to memory address : %04x\n", *sspdr_read_ptr);
/*
unsigned char i;
for (i = 0; i < 15; i++)
{
// consider leftmost bit
// set line high if bit is 1, low if bit is 0
if (data & 0x80)
output_high(SD_DI);
else
output_low(SD_DI);
// pulse clock to indicate that bit value should be read
output_low(SD_CLK);
output_high(SD_CLK);
// shift byte left so next bit will be leftmost
data <<= 1;
}
POKE8( (unsigned long)(memloc + 0x04), 0x00);
}
*/
close(fd);
}
--- In "yavin229" <> wrote:
>
>
>
> Hi all, I am really struggling to get communication working on my 7260 to a
> MAX6675 (Cold-Junction-Compensated K-Thermocouple-to-Digital Converter). I
> have gotten communication to onboard DIOs working and have modeled much of
> the register communication to the SPI after this. I am starting to wonder if
> my SPI hardware is even setup correctly as my queries to registries where my
> data should be returns data I write to the configuration registers. Are any
> drivers needed for communication to the spi? The configuration steps needed
> for a conversion are below and my program is attached (warning: I am
> programming noob :-) . Something that seems obviously wrong is that whatever
> configuration bits I set at regsiter location sspcr0 is the exact same data I
> read in at SSPDR (0x808a0008). I would expect 0's or changing temperature
> reading if this action was successfull. I am sure I am missing something
> simple. Thanks!
>
> ===== SSP Initialization Steps =====
> * Set the enable bit (SSE) in register SSPCR1
> * Write the other SSP configuration registers : SSPCR0 and SSPCPSR
> * Clear the enable bit (SSE) in register SSPCR1
> * Set the enable bit (SSE) in register SSPCR1
>
>
> ===== Max6675 Conversion Steps =====
> * Force CS high to start conversion
> * Force CS low to stop conversion
> * Apply clock signal to SO pin (SPI_MISO)
> * Read result from SO pin (SPI_MISO)
> * A complete serial interface read requires 16 clock cycles.
> Read the 16 output bits on the falling edge of the clock.
> The first bit, D15, is a dummy sign bit and is always
> zero. Bits D14?D3 contain the converted temperature in
> the order of MSB to LSB. Bit D2 is normally low and
> goes high when the thermocouple input is open. D1 is
> low to provide a device ID for the MAX6675 and bit D0
> is three-state
>
>
>
>
>
> Linux version 2.4.26-ts11 (gcc version 3.3.4) #215 Thu
> Jun 8 14:30:17 MST 2006
> CPU: Arm920Tid(wb) revision 0
> Machine: ep9301
> On node 0 totalpages: 2048
> zone(0): 2048 pages.
> zone(1): 0 pages.
> zone(2): 0 pages.
> On node 1 totalpages: 2048
> zone(0): 2048 pages.
> zone(1): 0 pages.
> zone(2): 0 pages.
> On node 4 totalpages: 2048
> zone(0): 2048 pages.
> zone(1): 0 pages.
> zone(2): 0 pages.
> On node 5 totalpages: 2048
> zone(0): 2048 pages.
> zone(1): 0 pages.
> zone(2): 0 pages.
> Kernel command line: console=ttyAM0,115200 root=/dev/hda1
> Relocating machine vectors to 0xffff0000
> Console: colour dummy device 80x30
> Calibrating delay loop... 99.94 BogoMIPS
> Memory: 8MB 8MB 8MB 8MB = 32MB total
> Memory: 28500KB available (1320K code, 350K data, 72K init)
> Dentry cache hash table entries: 4096 (order: 3, 32768 bytes)
> Inode cache hash table entries: 2048 (order: 2, 16384 bytes)
> Mount cache hash table entries: 512 (order: 0, 4096 bytes)
> Buffer cache hash table entries: 1024 (order: 0, 4096 bytes)
> Page-cache hash table entries: 8192 (order: 3, 32768 bytes)
> CPU: Testing write buffer: pass
> POSIX conformance testing by UNIFIX
> Linux NET4.0 for Linux 2.4
> Based upon Swansea University Computer Society NET3.039
> Initializing RT netlink socket
> Starting kswapd
> devfs: v1.12c (20020818) Richard Gooch
> devfs: boot_options: 0x1
> JFFS2 version 2.2. (C) 2001-2003 Red Hat, Inc.
> ttyAM0 at MMIO 0x808c0000 (irq = 52) is a AMBA
> ttyAM1 at MMIO 0x808d0000 (irq = 54) is a AMBA
> ttyAM2 at MMIO 0x808e0000 (irq = 55) is a AMBA
> pty: 1024 Unix98 ptys configured
> Serial driver version 5.05c (2001-07-08) with MANY_PORTS SHARE_IRQ enabled
> rtc: no TS-5620 RTC detected.
> ep93xx_eth() version: ep93xx_eth.c: V1.0 09/04/2003 Cirrus Logic
> Uniform Multi-Platform E-IDE driver Revision: 7.00beta4-2.4
> ide: Assuming 50MHz system bus speed for PIO modes; override with idebus=xx
> Technologic Systems TS-7XXX IDE initialization - driver version 1.3, 6/21/04.
> hda: SanDisk SDCFH-004G, CFA DISK drive
> ide0 at 0x8d000000-0x8d000007,0x88400006 on irq 32
> hda: attached ide-disk driver.
> hda: task_no_data_intr: status=0x51 { DriveReady SeekComplete Error }
> hda: task_no_data_intr: error=0x04 { DriveStatusError }
> hda: 7835184 sectors (4012 MB) w/1KiB Cache, CHS=7773/16/63
> Partition check:
> /dev/ide/host0/bus0/target0/lun0: [PTBL] [971/128/63] p1
> TS-7200 flash: Found 1 x16 devices at 0x0 in 16-bit bank
> Intel/Sharp Extended Query Table at 0x0031
> Using buffer write method
> cfi_cmdset_0001: Erase suspend on write enabled
> 0: offset=0x0,size=0x20000,blocks=128
> Creating 3 MTD partitions on "TS-7200 flash":
> 0x00000000-0x00020000 : "TS-BOOTROM"
> 0x00020000-0x00e20000 : "Linux"
> 0x00e20000-0x01000000 : "RedBoot"
> NET4: Linux TCP/IP 1.0 for NET4.0
> IP Protocols: ICMP, UDP, TCP, IGMP
> IP: routing cache hash table of 512 buckets, 4Kbytes
> TCP: Hash tables configured (established 2048 bind 4096)
> NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
> NetWinder Floating Point Emulator V0.97 (double precision)
> /dev/ide/host0/bus0/target0/lun0: p1
> /dev/ide/host0/bus0/target0/lun0: p1
> VFS: Mounted root (ext2 filesystem).
> Mounted devfs on /dev
> Freeing init memory: 72K
> VFS: Disk change detected on device 03:00
> /dev/ide/host0/bus0/target0/lun0: p1
> usb.c: registered new driver usbdevfs
> usb.c: registered new driver hub
> usb-ohci.c: USB OHCI at membase 0xe0020000, IRQ 56
> usb.c: new USB bus registered, assigned bus number 1
> hub.c: USB hub found
> hub.c: 3 ports detected
> :root# dmesg | grep -i spi
> :root# uname =-a
> Linux
> :root# uname -a
> Linux ts7000 2.4.26-ts11 #215 Thu Jun 8 14:30:17 MST 2006 armv4l GNU/Linux
>
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