FPGA revisions 0-2 had a problem with XUART channel #0 (stuck internal loopback)
FPGA version 4 is the most recent (less than 7 days old)
The FPGA can be reloaded post-bootup by ts7500ctl or you can send the board
back to us for reprogramming.
I have also updated the opencore source code for the TS-7500 and made it
available for download.
ftp://ftp.embeddedarm.com/ts-arm-sbc/ts-7500-linux/sources/fpga-opencore.zip
This opencore is the latest and contains the Lattice project files with Verilog
sources for the:
* TS-7500
* TS-7550
* TS-7552
* TS-4500
The TS-4500 is yet to be released, but we are releasing the opencore and
documentation before product release.
//Jesse Off
--- In "Jongsoo Kim" <> wrote:
>
> Group
>
>
>
>
>
> I am potentially seeing a strange thing in uart.
>
> It repeatedly read same character several time.
>
> I think it is xuart driver problem.
>
>
>
> I have FPGA revision 0x0.
>
>
>
> # ts7500ctl -i
> model=0x7550
> submodel=0x0
> revision=0x0
> bootmode=0x3
> bootdev=0x0
> resetsw_en=0x1
> latched_dio9=0x1
> dio=0x1ffffffffe0
> #
>
>
>
> I remember someone told me I have to watch out FPGA revision for TS7500.
>
>
>
> So the question is how I can upgrade FPGA revision?
>
>
>
> Thank you in advance
>
>
>
> Jongsoo
>
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