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[ts-7000] Re:U Sleep

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Subject: [ts-7000] Re:U Sleep
From: Rod Nussbaumer <>
Date: Sat, 21 Feb 2009 11:41:06 -0800
How are you reading the ADC? Most ADCs have a bit somewhere to signal 
End-of-Conversion. If your loop is simply reading a register that is 
supposed to contain converted data, but is not waiting for EoC, that 
would explain erratic readings. If a time-delay is inserted, as with 
usleep(), it would allow time for the conversion to complete, and 
provide you with valid readings. Again, this is consistent with the 
behavior you are seeing. Can you confirm that you are reading the ADC in 
a way that assures it has completed a conversion?
    ---   rod.


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