Hi Chris --
--- In "Christopher Friedt" <>
wrote:
> Checking out drivers/i2c/busses/i2c-gpio.c, I read that a udelay of 50
> corresponds to 10 kHz, and a udelay of 5 corresponds to 100 kHz. After
> checking out the patch for arch/arm/mach-ep93xx/core.c, I saw that
> the udelay field was set to 2. This leads me to conclude that the
> i2c-gpio on the TS boards, by default, have a bus frequency of 250
> kHz. Is that correct ??
>
> Taking a step back, all I really want or need in my I2C bus is 10 kHz,
> and my tests have shown that my el-cheapo, 2-transistor level-shifter
> has a unity amplitude response at 10 kHz. So I statically set my
> udelay to be 50, recompiled my kernel, and my level shifting circuit
> works perfectly now.
>
> Just a thought for the i2c-gpio kernel module ... maybe its a good
> idea for i2c-gpio module to accept a parameter, 'udelay=n', which
> would force a specified i2c bus frequency; 50=10kHz, 5==100kHz,
> 2==250kHz. A quick check of the module parameter would be easy to
> write up too.
>
> Does anybody know if i2c-core actually attempts to drive the bus at
> slower frequencies if a read or write op fails? A couple of times I've
> seen dmesg say that a read was successful on the 3rd attempt. If not,
> then accepting a timing parameter would certainly help.
Don't know if you've been working on this, or corresponding with H.
Sweeten, but he posted a patch which does allow a udelay override:
http://marc.info/?l=linux-arm-kernel&m=123489309408300&w=4
For now you can change the delay in your platform init code, but a
module parameter is a quite easy change now.
regards, ........ Charlie
>
> Any thoughts?
>
> Chris
>
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