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Hi, Indeed the FPGA content is properly restored at reboot, either a hard reset (power turning off and on) or a software one (reboot command). But, never try to configure the FPGA to give you access to the SPI EEPROM used for loading its initial structure, as a safety measure. Leave that EEPROM untouched or the "unbrickable design" mentioned on the TS-7800 page is no longer "unbrickable". As long as just the FPGA is reprogrammed and the SPI EEPROM is left untouched, everything is OK and will remain OK. Please also pay a lot of attention to the CPLD also on board as if touching it, effects are irreversible as well. Myself, I got to the point where I have my own code using directly the BIT files generated by the Lattice tools loaded into the FPGA. My current FPGA structure covers also some of the default TS devices, just basic ones so far, and, of course, my purpose specific structure. Also I have some minimal PCI bus mastering structure in the FPGA, though with simplified structure because the Marvell chip is allowing that (just one master and one target etc.). One more thing to remember! PCI clock (PCI_CLK signal) is generated by the FPGA. So check the schematics, use the 25MHz clock input, pass it through a PLL in the FPGA and generate 50MHz for PCI_CLK. One more hint, if you have another external master clock, use closest possible frequency just below 50MHz. One of my situations has 66MHz master clock and, multiplied by 3 and divided by 4, it gives 49.5MHz for PCI. These are just some tips and tricks. Many more will be made avaialble when possible, probably built around a wiki so other guys could come with extra info. Cheers, Catalin __._,_.___
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