2008/2/25, Kevin Cozens <>:
> Martin Guy wrote:
> > You'll find what you need in the ARM920T Technical Reference
> > Manual, section 12: "Instruction cycle summary".
>
> Thanks for the pointer, Martin. The ARM being a RISC based chip meant that
> the
> instruction set summary and timings is a little different than I'm used to
> seeing.
>
> A delay routine uses sub and bne. I didn't find a specific reference to
> either
> instruction in the manual. I took a guess that subs takes 1 cycle and bne
> takes 2 when the branch is taken and 1 when not.
Erm, sort of. Most ARM instructions take one cycle as long at the
program is going in a straight line because in each clock cycle it has
three or more instructions in its pipeline, all in various stages of
execution.
As I understand it, extra cycles of delay are incurred when one
instruction uses the result of the previous one (source register is
same as destination register of previous instr) and when branches
occur, since the speculatively half-execution of the next two or three
instructions has to be thrown away and the pipeline refilled starting
from the target of the jump.
Further, the pipeline behaviour varies from core design to core
design, since some have longer pipelines, up to 5 stages I think, and
later ones have more intelligent branch-prediction logic to help them
slew round corners without having to stop.
Then there is the question of whether the instructions are in the CPU
cache or have to be fetched from RAM... in the case of your tight loop
I guess that will not be an issue after the first cycle.
You best solution may be simply to time your code fragments on your
specific CPU - this is what the linux kernel does when it says
"Calibrating delay loop" - see calibrate_delay() in init/calibrate.c
and __delay() in arch/arm/lib/delay.S (in linux-2.6.23).
M
M
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