Hi,
I have been building a data logging system using the TS-7260. To save
power I use Jim Jacksons utility to slow my clock speed down to 20MHz.
At this reduced clock speed I can still get over 900 samples per
second from the ADC on the TS-7260. The only difficulty is that you
cannot rely of the 100Hz system clock to trigger every sample. In my
case I use simple time wasting loop routines to give me the delay
periods between the clock ticks as needed and check the clock about
every 10ms to make sure the sampling is on track. This requires extra
code compared to a simple trigger on each clock tick and some
experimenting to get the right delay loop setup. In my application it
is not critical that every sample is exactly timed to the ms. If this
is the same for you this method could be an option to recompiling the
OS to have a faster clock cycle.
Geoff Veale
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