Hi,
I've been playing around with Nios & Nios II cores on the 7300. A
couple of issues have arisen and I wondered if anyone else had been
exploring this area.
Some background: I've been evaluating the board for use in undergraduate
teaching and want to use the FPGA for a co-processor and/or stand-alone
designs as well as for co-design problems. Currently we use 2 separate
boards, an ARM based one and an Altera Apex20KE based one. Having a single
platform for teaching across several 2nd & 3rd year modules would be nice.
I have got both Nios & Nios II cores to run in the FPGA which I configured
via the JTAG interface. This includes accessing the SDRAM and implementing
2 uarts mapped to use the DIO pins, otherwise used for the VGA output. I
have a GERMS monitor running in both cores and communicating via the UART
to Altera's nios_run utility.
Read/write access to the SDRAM works for 32 bit and 16 bit access but
fails for 8 bit access, writing 8 bit values results in the value being
written to 2 consecutive locations. Modifying the GERMS monitor code
enables me to download srec files via the uart and then execute the
program from sdram provided there are no byte wide variables in the sdram.
This means that amongst other things remote debugging with gdb/insight
fails.
I notice that the schematic shows 12 address lines between the cyclone II
and the sdram even though there are only 11 addres pins on the sdram, the
12th goes to a pin marked as NC.
The SDRAM controller is the Altera supplied one from the SOPC-builder &
Nios dev kit. The Avalon bus, should be doing dynamic bus resizing when
accessing the memory.
Byte wide read/writes work correctly when using the FPGA's internal
memory.
We're using Quartus v6.0 + service pack and given other problems that
we've had with this release, I'm wondering if the problem lies with
Quartus.
Any suggestions ?
Secondly ;
Is there any way of using the I/O pins for the multiplexed uarts
directly from the FPGA? Studying the schematic seems to indicate that the
voltage shifters are enabled from the CPLD, so I guess that without
reconfiguring the CPLD ... bty I found that the I/O pins that connect to
the de/multiplexors need to be tri-stated when playing with the FPGA as
the '259 & '257 get rather hot otherwise.
I couldn't find the other end of wr_232, io126 on the fpga, so not sure
what this does either.
I would be grateful for any comments or suggestions as to any of the
above.
Regards,
Nigel Gunton
--
Senior Lecturer, School of Electrical & Computer Engineering,
Faculty of Computing, Engineering & Mathematical Sciences,
UWE, Bristol, UK
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