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My library was somewhat short on details of the signal levels on the PC104 bus, so I did some experiments. Here are the results. I'm trying to write this in monospaced font so that it the tables below are readable. I did not pay close attention to the actual timing. I was more interested in signals levels. IO and Memory accesses seem to have the same characteristics. In the table below, Access is the size of the variable being read or written. Port is the size of the hardware port, as determined by the address used in the mmap() call. This was done on a TS-7250. In the case of expanded cycles or the address bus changing in the middle of the cycle, the address increments by 1 for the byte ports and 2 for the short ports. Access Port R/W BHE# Byte Byte W 1 Data on DL Byte Byte R 0 Data on DL Short Byte W 11 Data on DL, Expanded to two cycles Short Byte R 0 Data on DL, One long cycle with the address changing in the middle Long Byte W 1111 Data on DL, Expanded to four cycles Long Byte R 0 Data on DL, One long cycle with the address changing 3 times Byte Short W ~A0 Data for even addresses appears on DL, BHE#=1 Data for odd addresses appears on DH, BHE#=0 Byte Short R 0 Data for even addresses read from DL, I'm not sure about odd addresses Short Short W 0 Data on { DH, DL } Short Short R 0 Data on { DH, DL } Long Short W 00 Data on { DH, DL }, expanded to two cycles Long Short R 0 Data on {DH, DL}, address changes in middle of long cycle Key: Byte 8 bits Short 16 bits Long 32 bits R Read W Write DL Data bits D7..D0 DH Data bits D15..D8 Notes: I did not try non aligned transfers (short access to odd short port) I do not know whether the read cycles with the address changing in the middle would work properly if the data changed, because my prototype doesn't change the data when the address changes. I don't know which half of the data bus is active for a byte read from an odd short port address, because I drive the same value to both halves of the data bus in this case. The expanded cycles (i.e. long write to byte port) occur very quickly, that is with reduced time between memory cycles. Read cycles seem to always have BHE#=0. This seems incorrect to me. I just happen to still have the 16-bit IO port accesses on my logic analyzer, so let's see, how long are the cycles? Read cycles 270 nS Write cycles 280 nS Read cycle, long data, 600 nS Rich -- Rich Wilson __._,_.___
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