[ts-7000] Re: Parking the KS8721 FPGA Ethernet Interface

["waggywagz" <>]

> If someone has it handy, could you post the verilog (or even just the
> signal levels) needed, to safely "park" the FPGA ethernet KS8721 chip
> when it is not needed?  If it has not already been done, I can
> cross-reference the KS8721 datasheet, the TS-7300 schematic, and the
> ts7300_top.v source and post the resulting verilog here for review. 
> If there are any 'gotchas' about turning off the KS8721, I would
> appreciate finding out in advance.

I modified ts7300_top.v as follows to temporarily park eth1 when using
a custom bitstream.  So far no gotchas after a few weeks of using it,
and eth1 works fine when the default bitstream is loaded.  The full
compilation time of a graphic LCD driver core is cut by 80% with eth1
temporarily parked, a significant improvement in development cycle time.

I am not certain where to post the full code using conditional
compilation blocks (`define... `ifdef ... `else), and will simply
describe equivalent modifications here.  All line numbers refer to the
original opencores ts7300_top.v.

Comment out or skip lines 488-508, 516-563, and 685.
...
488] wb32_blockram #(.endian_swap(1'b1)) ethramcore(
...
507]   .wb1_ack_o(ethwbm_ack_i)
508] );
...
516] eth_top ethcore(
...
562]   ethcore_mdoe_q <= ethcore_mdoe;
563] end
...
684] /* PHY always on */
685] assign eth_pd_pad = 1'b1;
...

Add the following after line 563:
...
562]   ethcore_mdoe_q <= ethcore_mdoe;
563] end

assign   eth_mdc_pad = 1'b0; //FPGA output
assign eth_txdat_pad = 4'b0; //FPGA output
assign  eth_txen_pad = 1'b0; //FPGA output
assign eth_txerr_pad = 1'b0; //FPGA output
assign    eth_pd_pad = 1'b0; //FPGA output: turn off eth2

//prevent hanging if cpu attempts access
assign    ethcore_ack = wb32m_cyc_o &&    ethcore_stb; /* 0-wait state
WISHBONE */
assign ethramcore_ack = wb32m_cyc_o && ethramcore_stb; /* 0-wait state
WISHBONE */

565] wire [31:0] usercore_dat;
566] wire usercore_ack;
...


Hope this helps.
-David





 
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