Poke 16 bit value 0x2 (least 3 bits significant) to 0x22c00000
//Jesse Off
--- In Curtis Monroe <> wrote:
>
> Whats the location of this magic bit?
>
> -Curtis.
>
> On February 12, 2006 11:12 am, Jesse Off wrote:
> > The real frequency is 14.3 Mhz, but the CPLD gets it by dropping every
> > 32nd clock tick from 14.7456Mhz. This works, but its probably too
> > high of a jitter to feed a PLL so there is a magic bit in a register
> > that you can use to disable this behavior and get a clean 14.7456Mhz.
> >
> > //Jesse Off
> >
> >
> > --- In Rich Wilson <richaw@> wrote:
> > >
> > > I'm doing some planning, but haven't purchased a TS-7250 yet, so
> > > I can't measure this myself.
> > >
> > > The TS-7250 User's Manual page 26 shows the frequency of the
> > > PC104 bus signal OSC to be 14.3 MHz.
> > >
> > > The TS-7250 schematic shows this pin to be connected to the
> > > signal ISA_OSC, which apparently comes from U19, a Xilinx
> > > CPLD. I see no other connection to this signal on the schematic.
> > > The Xilinx clock input is 14.74 MHz.
> > >
> > > I'm highly suspicious that U19 is not capable of converting from
> > > 14.74MHz to 14.3 MHz, and that there may be a documentation
> > > error here somewhere. What's the real frequency of the ISA
> > > OSC pin?
> > >
> > > Thanks.
> > >
> > > Rich
> > > --
> > > Rich Wilson
> > > richaw@
> > > 425-337-7129
> > >
> >
> >
> >
> >
> >
> >
> >
> >
> > Yahoo! Groups Links
> >
> >
> >
> >
> >
> >
> >
> >
>
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