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| Subject: | [ts-7000] Re: FCLK, HCLK and PCLK on TS7250 ? |
| From: | "BxWen" <> |
| Date: | Tue, 21 Feb 2006 21:20:53 -0000 |
--- In Jim Jackson <> wrote: > down load.... > > http://www.comp.leeds.ac.uk/jj/linux/cctl-0.1beta.tgz > > and run the cctl program, it will list the current register settings and > decode them for you. You can also use it to alter various fields in the > registers. > > Jim > Jim: Thank you very much. It seems that PCLK is at 50MHz. I can generate a square wave at a DIO pin of ~6.5Mhz. Which means ~4 PCLK cycle for a LDR operation. 6.5 x 4 x 2 ~ 52Mhz. A little disappointed by the APB throughput. Bing Yahoo! Groups Links <*> To visit your group on the web, go to: http://groups.yahoo.com/group/ts-7000/ <*> To unsubscribe from this group, send an email to: <*> Your use of Yahoo! Groups is subject to: http://docs.yahoo.com/info/terms/ |
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